EmuZWin built-in ZX Assembler
supported operators and directives.

(Ñ) by Vladimir Kladov, 2003

Starting from v2.2, it is possible to view entire list of all operators and directives, supported by the built-in ZX Assembler, directly in assembler window.

Source code should satisfy following rules to be compiled correcly.

Following directives and assembler statements are supported by internal assembler. (Character '#' used to note that an operand could be of any numeric expression allowed).


ORG [{ RAMn | ROMn },] #target_address [, #dest_address ]
Defines target assembling address and target output destination address.
RAMn and ROMn is used to define RAM bank (n=0..7) or ROM bank (n=0..1).
If distinct dest_address is defined, compiled bytes are put to that address,
though a code itself is compiled for target_address.
label: EQU #expression
Defines constant label equal to given expression.
DEFB [{ #expression | 'string' }] [, [{ #expression | 'string' }] ]...
a list of bytes. For a string, for each character a single byte is
generated always. So, DEFB 'abc',0 will be compiled to 4 bytes 
61h,62h,63h,0.
DEFW [{ #expression }] [, [{ #expression }] ]
a list of 16-bit words.

Alphabetical list of commands.
ADD HL, { BC | DE | HL | SP }
ADD IX, { BC | DE | IX | SP }
ADD IY, { BC | DE | IY | SP }
ADD [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
ADC HL, { BC | DE | HL | SP }
ADC IX, { BC | DE | IX | SP }
ADC IY, { BC | DE | IY | SP }
ADC [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
AND [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
BIT #number, { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) }
BIT #number, { (IX±#offset ) | (IY±#offset) },
             { B | C | D | E | H | L | A }
CALL [ { NZ | Z | NC | C | PO | PE | P | M }, ] #address
CCF
CP  [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
CPD
CPDR
CPI
CPDR
DI
DJNZ #address
EI
EX AF, AF'
EX DE, { HL | IX | IY }
EX (SP), { HL | IX | IY }
EXX
HALT
IM0 | IM1 | IM2 | IM #n
IN [ A, ] { (#port) | (C) }
IN { B | C | D | E | H | L | F | A }, (C)
IND
INDR
INI
INIR
JP [ { NZ | Z | NC | C | PO | PE | P | M }, ] #address
JR [ { NZ | Z | NC | C }, ] #address
LD A, { I | R | B | C | D | E | H | L | M | (HL ) | A | 
        #expression | IXH | IXL | IYH | IYL | 
       (IX±#offset) | (IY±#offset) | (BC) | (DE) | (#address) }
LD { B | C | D | E | H | L | M | (HL) }, 
   { B | C | D | E | H | L | M | A | #expression }
LD { B | C | D | E | IXH | IXL | A | (IX±#offset) },
   { B | C | D | E | IXH | IXL | A | #expression }
LD { B | C | D | E | IYH | IYL | A | (IY±#offset) },
   { B | C | D | E | IYH | IYL | A | #expression }
LD { B | C | D | E | IXH | IXL | A },
   { B | C | D | E | IXH | IXL | A | (IX±#offset) }
LD { B | C | D | E | IYH | IYL | A },
   { B | C | D | E | IYH | IYL | A | (IY±#offset) }
LD { I | R }, A
LD { BC | DE | HL | SP | IX | IY }, { #expression | ( #address ) }
LD ( #address ), { BC | DE | HL | SP | IX | IY }
LDD
LDDR
LDI
LDIR
NEG
NOP
OR  [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
OUT { (#port) | (C) } [, A ]
OUT (C), { B | C | D | E | H | L | F | A }
OUTD
OTDR
OUTI
OTIR
POP  { BC | DE | HL | AF | IX | IY }
PUSH { BC | DE | HL | AF | IX | IY }
RET [ { NZ | Z | NC | C | PO | PE | P | M | N | I } ]
RETI
RETN
RES #number, { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) }
RES #number, { (IX±#offset ) | (IY±#offset) },
             { B | C | D | E | H | L | A }
RLA
RL  { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
RLCA
RLC { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
RLD
RRA
RR  { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
RRCA
RRC { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
RRD
RST #expression ;
    (allowed following values: 
     0..7, 8, 16, 24, 32, 40, 48, 56)
SBC HL, { BC | DE | HL | SP }
SBC [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
SCF
SET #number, { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) }
SET #number, { (IX±#offset ) | (IY±#offset) },
             { B | C | D | E | H | L | A }
SLA { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
SLA { (IX±#offset ) | (IY±#offset) },
    { B | C | D | E | H | L | A }
SLI { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
SLI { (IX±#offset ) | (IY±#offset) },
    { B | C | D | E | H | L | A }
SLL { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
SLL { (IX±#offset ) | (IY±#offset) },
    { B | C | D | E | H | L | A }
SRL { B | C | D | E | H | L | M | (HL) | A | 
    IXH | IXL | (IX±#offset ) | (IY±#offset) }
SRL { (IX±#offset ) | (IY±#offset) },
    { B | C | D | E | H | L | A }
SUB [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }
XOR [ A, ] { B | C | D | E | H | L | M | (HL) | A | 
             IXH | IXL | (IX±#offset ) | (IY±#offset) |
             #expression }

Last update: 3-Nov-2003

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